In large flexible software systems, bloat occurs in many forms, causing excess resource utilization and resource bottlenecks. This results in lost throughput and wasted joules. However, mitigating bloat is not easy; efforts are best applied where savings would be substantial. To aid this we develop an analytical model establishing the relation between bottleneck in resources, bloat, performance and power.

Analyses with the model places into perspective results from the first experimental study of the power- performance implications of bloat. In the experiments we find that while bloat reduction can provide as much as 40% energy savings, the degree of impact depends on hardware and software characteristics. We confirm predictions from our model with selected results from our experimental study.

Our findings show that a software-only view is inadequate when assessing the effects of bloat. The impact of bloat on physical resource usage and power should be understood for a full systems perspective to properly deploy bloat reduction solutions and reap their power-performance benefits.

While sleep states have existed for mobile devices and workstations for some time, these sleep states have largely not been incorporated into the servers in today's data centers.

Chip designers have been unmotivated to design sleep states because data center administrators haven’t expressed any desire to have them. High setup times make administrators fearful of any form of dynamic power management, whereby servers are suspended or shut down when load drops. This general reluctance has stalled research into whether there might be some feasible sleep state (with sufficiently low setup overhead and/or sfficiently low power) that would actually be beneficial in data centers.

This paper uses both experimentation and theory to investigate the regime of sleep states that should be advantageous in data centers. Implementation experiments involve a 24-server multi-tier testbed, serving a web site of the type seen in Facebook or Amazon with key-value workload and a range of hypothetical sleep states. Analytical modeling is used to understand the effect of scaling up to larger data centers. The goal of this research is to encourage data center administrators to consider dynamic power management and to spur chip designers to develop useful sleep states for servers.

Recent proposals using low-power processors and Flash-based storage can dramatically improve the energy-efficiency of compute and storage subsystems in data-centric computing. However, in a balanced system design, these changes call for matching improvement in the network subsystem as well. Conventional Ethernet-based networks are a potential energy-efficiency bottleneck due to the limited performance of gigabit Ethernet and the high power overhead of 10-gigabit Ethernet. In this paper, we evaluate the benefits of using an alternative, high-bandwidth, low-power, interconnect—PCIe—for power-efficient networking. Our experiments using PCIe’s Non-Transparent Bridging for data transfer demonstrate significant performance gains at lower power, leading to 60-124% better energy efficiency. Early experiences with PCIe clustering also point to several challenges of PCIe-based networks and new opportunities for low-latency power-efficient datacenter networking.

In recent years, there has been a rapid evolution of energy-aware computing systems (e.g., mobile devices, wireless sensor nodes), as still rising system complexity and increasing user demands make energy a permanently scarce resource. While static and dynamic optimizations for energy-aware execution have been massively explored, writing energy-efficient programs in the first place has only received limited attention.

This paper proposes SEEP, a framework which exploits symbolic execution and platform-specific energy profiles to provide the basis for energy-aware programming. More specifically, the framework provides developers with information about the energy demand of their code at hand, even for the invocation of library functions and in settings with multiple possibly strongly heterogeneous target platforms. This equips developers with the necessary knowledge to take energy demand into account during the task of writing programs.

As brown energy costs grow, renewable energy becomes more widely used. Previous work focused on using immediately available green energy to supplement the non-renewable, or brown energy at the cost of canceling and rescheduling jobs whenever the green energy availability is too low. In this paper we design an adaptive data center job scheduler which utilizes short term prediction of solar and wind energy production. This enables us to scale the number of jobs to the expected energy availability, thus reducing the number of cancelled jobs by 4x and improving green energy usage efficiency by 3x over just utilizing the immediately available green energy.

Scalability challenges of DRAM technology call for advances in emerging memory technologies, among which Phase Change Memory (PCM) has received considerable attention due to its non-volatility, storage density and capacity advantages. The drawbacks of PCM include limited write endurance and high power consumption for write operations (upto 10x in comparison to read operations). In this paper, we investigate new techniques that would perform writes to PCM with energy awareness. Our results show that we can minimize the write energy consumption by up to 8.1x by simply converting PCM native writes to read-before-write, and upto an additional 22.9% via intelligent out-of-position updates.

Realizing highly available datacenter power infrastructure is an extremely expensive proposition with costs more than doubling as we move from three 9’s (Tier-1) to six 9’s (Tier-4) of availability. Existing approaches only consider the cost/availability trade-off for a restricted set of power infrastructure configurations, relying mainly on component redundancy. A number of additional knobs such as centralized vs. distributed component placement and power-feed interconnect topology also exist, whose impact has only been studied in limited forms. In this paper, we develop detailed datacenter availability models using Continuous-time Markov Chains and Reliability Block Diagrams to quantify the cost-availability trade-off offered by these power infrastructure knobs.

The electricity cost of cooling systems can account for 30% of the total electricity bill of operating a data center. While many prior studies have tried to reduce the cooling energy in data centers, they cannot effectively utilize the time-varying power prices in the power market to cut the electricity bill of data center cooling. Thermal storage techniques have provided opportunities to store cooling energy in ice or water-based tanks or overcool the data center when the power price is relatively low. Consequently, when the power price is high, data centers can choose to use less electricity from power grid for cooling, resulting in a significantly reduced electricity bill.

In this paper, we design and evaluate TStore, a cooling strategy that leverages thermal storage to cut the electricity bill for cooling, without causing servers in a data center to overheat. TStore checks the low prices in the hour-ahead power market and overcools the thermal masses in the datacenter, which can then absorb heat when the power price increases later. On a longer time scale, TStore is integrated with auxiliary thermal storage tanks, which are recently adopted by some data centers to store energy in the form of ice when the power price is low at night, such that the stored ice can be used to cool the data center in daytime. We model the impacts of TStore on server temperatures based on Computational Fluid Dynamics (CFD) to consider the realistic thermal dynamics in a data center with 1,120 servers. We then evaluate TStore using workload traces from real-world data centers and power price traces from a real power market. Our results show that TStore achieves the desired cooling performance with a 16.8% less electricity bill than the current practice.

Harvested energy makes long-term maintenance-free sensor deployments possible; however, as devices shrink in order to accommodate new applications, tightening energy budgets and increasing power supply volatility leaves system designers poorly equipped to predict how their devices will behave when deployed.

This paper describes the design and initial FPGA-based implementation of Ekho, a tool that records and emulates energy harvesting conditions, in order to support realistic and repeatable testing and experimentation. Ekho uses the abstraction of I-V curves—curves that describe harvesting current with respect to supply voltage—to accurately represent harvesting conditions, and supports a range of harvesting technologies. An early prototype emulates I-V curves with 0.1mA accuracy, and responds in 4.4µs to changes in energy conditions.

In recent years, power consumption has become one of the most important design criteria for microprocessors. CPUs are therefore no longer developed with a narrow focus on raw compute performance. This means that well-established processor features that have proven to increase compute performance now need to be re-evaluated with a new focus on energy efficiency. This paper presents an energy efficiency evaluation of the symmetric multithreading (SMT) feature on state-of-the-art x86_64 processors. We use a mature power measurement methodology to analyze highly sophisticated low-level microbenchmarks as well as a diverse set of application benchmarks. Our results show that—depending on the workload—SMT can be at the same time advantageous in terms of performance and disadvantageous in terms of energy efficiency. Moreover, we demonstrate how the SMT effciency has advanced between two processor generations.